Electronic systems typically employ several different types of electrical interconnecting apparatus having planar layers of electrically conductive material separated by dielectric layers. Some of the conductive layers may be patterned to form electrically conductive signal lines or “traces” to different layers to provide electrical contacts between signals, power and ground terminals. For example, integrated circuits typically have several layers of conductive traces which interconnect electronic devices formed upon and within a semiconductor substrate. Additionally, these electrical traces may be used to electrically connect to pins or leads of the integrated circuits. These pins and leads may then be coupled to a multi-layer ceramic substrate or device package that provide intermediate routing from the integrated circuit pins to terminals of a printed circuit board (PCB). The PCB also typically includes several layers of conductive traces separated by dielectric layers. The conductive traces are used to electrically interconnect terminals of electronic devices mounted upon the PCB.
Signal frequencies of digital electronic systems are continually increasing. In multi-layer structures (e.g., printed wire boards, ceramic substrates, and/or semiconductor structures), the influence of inductance, capacitance and resistance of the grid (e.g., cell areas of different physical layers of the die and package) have significant effects on the integrity of the digital electronic system as frequencies increase. The effects can include including signal degradation due to reflections, power supply “droop”, ground “bounce”, and increased electromagnetic emissions. One technique for mitigating power supply droop is the placement of “bypass” or “decoupling” capacitors. The bypass capacitor supplies a substantial amount of the transient load current, thereby reducing the amount of transient load current flowing through the power supply conductors. Determining the proper values, the locations and the optimum number of bypass capacitors for one or more multi-layer structures has been a “trial and error” process.